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d a t a sh eet product speci?cation supersedes data of 1998 oct 02 file under integrated circuits, ic06 1998 nov 10 integrated circuits 74hc/hct4066 quad bilateral switches for a complete data sheet, please also download: the ic06 74hc/hct/hcu/hcmos logic family specifications
1998 nov 10 2 philips semiconductors product speci?cation quad bilateral switches 74hc/hct4066 features very low on resistance: 50 w (typ.) at v cc = 4.5 v 45 w (typ.) at v cc = 6.0 v 35 w (typ.) at v cc = 9.0 v output capability: non-standard i cc category: ssi. general description the 74hc/hct4066 are high-speed si-gate cmos devices and are pin compatible with the 4066 of the 4000b series. they are specified in compliance with jedec standard no. 7a. the 74hc/hct4066 have four independent analog switches. each switch has two input/output terminals (ny, nz) and an active high enable input (ne). when ne is low the belonging analog switch is turned off. the 4066 is pin compatible with the 4016 but exhibits a much lower on resistance. in addition, the on resistance is relatively constant over the full input signal range. quick reference data gnd = 0 v; t amb =25 c; t r =t f =6ns notes 1. c pd is used to determine the dynamic power dissipation (p d in m w): a) p d =c pd v cc 2 f i +? {(c l + c s ) v cc 2 f o } where: b) f i = input frequency in mhz c) f o = output frequency in mhz d) ? {(c l + c s ) v cc 2 f o } = sum of outputs e) c l = output load capacitance in pf f) c s = maximum switch capacitance in pf g) v cc = supply voltage in v 2. for hc the condition is v i = gnd to v cc for hct the condition is v i = gnd to v cc - 1.5 v symbol parameter conditions typical unit hc hct t pzh / t pzl turn-on time ne to v os c l = 15 pf; r l =1k w ; v cc = 5 v 11 12 ns t phz / t plz turn-off time ne to v os 13 16 ns c i input capacitance 3.5 3.5 pf c pd power dissipation capacitance per switch notes 1 and 2 11 12 pf c s max. switch capacitance 8 8 pf
1998 nov 10 3 philips semiconductors product speci?cation quad bilateral switches 74hc/hct4066 ordering information pin description type number package name description version 74hc4066 dip14 plastic dual in-line package; 14 leads (300 mil) sot27-1 74hc4066 so14 plastic small outline package; 14 leads; body width 3.9 mm sot108-1 74hc4066 ssop14 plastic shrink small outline package; 14 leads; body width 5.3 mm sot337-1 74hc4066 tssop14 plastic thin shrink small outline package; 14 leads; body width 4.4 mm sot402-1 74hct4066 dip14 plastic dual in-line package; 14 leads (300 mil) sot27-1 74hct4066 so14 plastic small outline package; 14 leads; body width 3.9 mm sot108-1 74hct4066 ssop14 plastic shrink small outline package; 14 leads; body width 5.3 mm sot337-1 74hct4066 tssop14 plastic thin shrink small outline package; 14 leads; body width 4.4 mm sot402-1 pin no. symbol name and function 1, 4, 8, 11 1y to 4y independent inputs/outputs 2, 3, 9, 10 1z to 4z independent inputs/outputs 7 gnd ground (0 v) 13, 5, 6, 12 1e to 4e enable inputs (active high) 14 v cc positive supply voltage fig.1 pin configuration. handbook, halfpage mgr253 4066 1 2 3 4 5 6 7 8 14 13 12 11 10 9 1y 1z 2z 2y 2e 3e gnd 3y 3z 4z 4y 4e 1e v cc fig.2 logic symbol. handbook, halfpage mgr254 13 1 1y 2 1z 4 2y 3 2z 8 3y 9 3z 11 4y 10 4z 1e 52e 63e 12 4e
1998 nov 10 4 philips semiconductors product speci?cation quad bilateral switches 74hc/hct4066 handbook, halfpage mgr255 13 # 5# 6# 12 # 1 2 4 3 8 9 11 10 handbook, halfpage mgr256 13 # 5# 6# 12 # 1 11 x1 11 x1 11 x1 11 x1 2 4 3 8 9 11 10 fig.3 iec logic symbol. a. b. fig.4 functional diagram. handbook, halfpage mgr257 11 4y 12 4e 4z 10 3z 9 2z 3 1z 2 8 3y 6 3e 4 2y 5 2e 1 1y 13 1e function table note 1. h = high voltage level; l = low voltage level. input ne switch loff hon fig.5 schematic diagram (one switch). handbook, halfpage mgr258 v cc gnd ne nz ny v cc
1998 nov 10 5 philips semiconductors product speci?cation quad bilateral switches 74hc/hct4066 ratings limiting values in accordance with the absolute maximum system (iec 134) voltages are referenced to gnd (gnd=0v) note 1. to avoid drawing v cc current out of terminal nz, when switch current flows in terminal ny, the voltage drop across the bidirectional switch must not exceed 0.4 v. if the switch current flows into terminal nz, no v cc current will flow out of terminal ny. in this case there is no limit for the voltage drop across the switch, but the voltages at ny and nz may not exceed v cc or gnd. recommended operating conditions symbol parameter min. max. unit conditions v cc dc supply voltage - 0.5 +11.0 v i ik dc digital input diode current 20 ma for v i <- 0.5 v or v i > v cc + 0.5 v i sk dc switch diode current 20 ma for v s <- 0.5 v or v s > v cc + 0.5 v i is dc switch current 25 ma for - 0.5 v < v s < v cc + 0.5 v i cc; i gnd dc v cc or gnd current 50 ma t stg storage temperature range - 65 +150 c p tot power dissipation per package for temperature range: - 40 to +125 c 74hc/hct plastic dil 750 mw above +70 c: derate linearly with 12 mw/k plastic mini-pack (so) 500 mw above +70 c: derate linearly with 8 mw/k p s power dissipation per switch 100 mw symbol parameter 74hc 74hct unit conditions min. typ. max. min. typ. max. v cc dc supply voltage 2.0 5.0 10.0 4.5 5.0 5.5 v v i dc input voltage range gnd v cc gnd v cc v v s dc switch voltage range gnd v cc gnd v cc v t amb operating ambient temperature range - 40 +85 - 40 +85 c see dc and ac characteristics t amb operating ambient temperature range - 40 +125 - 40 +125 c t r ,t f input rise and fall times 6.0 1000 6.0 500 ns v cc = 2.0 v 500 v cc = 4.5 v 400 v cc = 6.0 v 250 v cc = 10.0 v
1998 nov 10 6 philips semiconductors product speci?cation quad bilateral switches 74hc/hct4066 dc characteristics for 74hc/hct for 74hc: v cc = 2.0, 4.5, 6.0 and 9.0 v; for 74hct: v cc = 4.5 v note 1. at supply voltages approaching 2 v, the analog switch on-resistance becomes extremely non-linear. therefore it is recommended that these devices be used to transmit digital signals only, when using these supply voltages. symbol parameter t amb ( c) unit test conditions 74hc/hct v cc (v) i s ( m a) v is v i +25 - 40 to +85 - 40 to +125 min. typ. max. min. max. min. max. r on on-resistance (peak) -- - - w 2.0 100 v cc to gnd v ih or v il 54 95 118 142 w 4.5 1000 42 84 105 126 w 6.0 1000 32 70 88 105 w 9.0 1000 r on on-resistance (rail) 80 ---w 2.0 100 gnd v ih or v il 35 75 95 115 w 4.5 1000 27 65 82 100 w 6.0 1000 20 55 70 85 w 9.0 1000 r on on-resistance (rail) 100 ---w 2.0 100 v cc v ih or v il 42 80 106 128 w 4.5 1000 35 75 94 113 w 6.0 1000 27 60 78 95 w 9.0 1000 d r on maximum variation of on-resistance between any two channels -w 2.0 v cc to gnd v ih or v il 5 w 4.5 4 w 6.0 3 w 9.0
1998 nov 10 7 philips semiconductors product speci?cation quad bilateral switches 74hc/hct4066 fig.6 test circuit for measuring on-resistance (r on ). d book, full pagewidth mgr259 v ny nz i is v is = 0 to v cc - gnd high (from enable inputs) gnd fig.7 test circuit for measuring off-state current. handbook, full pagewidth mgr260 a a ny nz v i = v cc or gnd v o = gnd or v cc low (from enable inputs) gnd fig.8 test circuit for measuring on-state current. handbook, full pagewidth mgr261 a a ny nz v i = v cc or gnd v o (open circuit) high (from enable inputs) gnd
1998 nov 10 8 philips semiconductors product speci?cation quad bilateral switches 74hc/hct4066 fig.9 typical on-resistance (r on ) as a function of input voltage (v is ) for v is = 0 to v cc . handbook, halfpage 09 60 10 20 mgr262 30 40 50 1.8 3.6 5.4 7.2 v is (v) r on ( w ) 6 v 9 v v cc = 4.5 v
1998 nov 10 9 philips semiconductors product speci?cation quad bilateral switches 74hc/hct4066 dc characteristics for 74hc voltage are referenced to gnd (ground = 0 v) symbol parameter t amb ( c) unit test conditions 74hc v cc (v) v i other +25 - 40 to +85 - 40 to +125 min. typ. max. min. max. min. max v ih high-level input voltage 1.5 1.2 1.5 1.5 v 2.0 3.15 2.4 3.15 3.15 4.5 4.2 3.2 4.2 4.2 6.0 6.3 4.7 6.3 6.3 9.0 v il low-level input voltage 0.8 0.50 0.50 0.50 v 2.0 2.1 1.35 1.35 1.35 4.5 2.8 1.80 1.80 1.80 6.0 4.3 2.70 2.70 2.70 9.0 i i input leakage current 0.1 1.0 1.0 m a 6.0 v cc or gnd 0.2 2.0 2.0 10.0 i s analog switch off-state current per channel 0.1 1.0 1.0 m a 10.0 v ih or v il v s =v cc - gnd (see fig.7) i s analog switch on-state current 0.1 1.0 1.0 m a 10.0 v ih or v il v s =v cc - gnd (see fig.8) i cc quiescent supply current 2.0 20.0 40.0 m a 6.0 v cc or gnd v is = gnd or v cc ; v os =v cc or gnd 4.0 40.0 80.0 10.0
1998 nov 10 10 philips semiconductors product speci?cation quad bilateral switches 74hc/hct4066 ac characteristics for 74hc gnd = 0 v; t r =t f = 6 ns; c l =50pf symbol parameter t amb ( c) unit test conditions 74hc v cc (v) other +25 - 40 to +85 - 40 to +125 min. typ. max. min. max. min. max. t phl /t plh propagation delay v is to v os 8 60 75 90 ns 2.0 r l = ; c l =50pf (see fig.18) 3 12 15 18 4.5 2 10 13 15 6.0 2 8 10 12 9.0 t pzh /t pzl turn-on time ne to v os 36 100 125 150 ns 2.0 r l =1k w ; c l =50pf (see figs 19 and 20) 13 20 25 30 4.5 10 17 21 26 6.0 8 13 16 20 9.0 t phz /t plz turn-off time ne to v os 44 150 190 225 ns 2.0 r l =1k w ; c l =50pf (see figs 19 and 20) 16 30 38 45 4.5 13 26 33 38 6.0 16 24 16 20 9.0
1998 nov 10 11 philips semiconductors product speci?cation quad bilateral switches 74hc/hct4066 dc characteristics for 74hct voltages are referenced to gnd (ground = 0 v) note 1. the value of additional quiescent supply current ( d i cc ) for a unit load of 1 is given here. to determine d i cc per input, multiply this value by the unit load coefficient shown in the table below. table 1 symbol parameter t amb ( c) unit test conditions 74hct v cc (v) v i other +25 - 40 to +85 - 40 to +125 min. typ. max. min. max. min. max. v ih high-level input voltage 2.0 1.6 2.0 2.0 v 4.5 to 5.5 v il low-level input voltage 1.2 0.8 0.8 0.8 v 4.5 to 5.5 i i input leakage current 0.1 1.0 1.0 m a 5.5 v cc or gnd i s analog switch off-state current per channel 0.1 1.0 1.0 m a 5.5 v ih or v il v s =v cc - gnd (see fig.7) i s analog switch on-state current 0.1 1.0 1.0 m a 5.5 v ih or v il v s =v cc - gnd (see fig.8) i cc quiescent supply current 2.0 20.0 40.0 m a 4.5 to 5.5 v cc or gnd v is = gnd or v cc ; v os =v cc or gnd d i cc additional quiescent supply current per input pin for unit load coef?cient is 1 (note 1) 100 360 450 490 m a 4.5 to 5.5 v cc - 2.1 v other inputs at v cc or gnd input unit load coefficient ne 1.00
1998 nov 10 12 philips semiconductors product speci?cation quad bilateral switches 74hc/hct4066 ac characteristics for 74hct gnd = 0 v; t r =t f =6ns additional ac characteristics for 74hc/hct recommended conditions and typical values gnd = 0 v; t r =t f =6ns notes 1. v is is the input voltage at ny or nz terminal, whichever is assigned as an input. 2. v os is the output voltage at ny or nz terminal, whichever is assigned as an output. 3. adjust input voltage v is is 0 dbm level (0 db m = 1 mw into 600 w ). 4. adjust input voltage v is is 0 dbm level at v os for 1 mhz (0 db m = 1 mw into 50 w ). symbol parameter t amb ( c) unit test conditions 74hct v cc (v) other +25 - 40 to +85 - 40 to +125 min. typ. max. min. max. min. max. t phl /t plh propagation delay v is to v os 3 12 15 18 ns 4.5 r l = ;c l =50pf (see fig.18) t pzh /t pzl turn-on time ne to v os 12 24 30 36 ns 4.5 r l =1k w ; c l =50pf (see figs 19 and 20) t phz /t plz turn-off time ne to v os 20 35 44 53 ns 4.5 r l =1k w ; c l =50pf (see figs 19 and 20) symbol parameter typ. unit v cc (v) v is(p - p) (v) conditions sine wave distortion f = 1 khz 0.04 % 4.5 4.0 r l =10k w ; c l =50pf (see fig.16) 0.02 % 9.0 8.0 sine wave distortion f = 10 khz 0.12 % 4.5 4.0 r l =10k w ; c l =50pf (see fig.16) 0.06 % 9.0 8.0 switch off signal feed-through - 50 db 4.5 note 3 r l = 600 w ; c l = 50 pf; f = 1 mhz (see figs 10 and 17) - 50 db 9.0 crosstalk between any two switches - 60 db 4.5 note 3 r l = 600 w ; c l = 50 pf; f = 1 mhz (see fig.12) - 60 db 9.0 v (p - p) crosstalk voltage between enable or address input to any switch (peak-to-peak value) 110 mv 4.5 r l = 600 w ; c l = 50 pf; f = 1 mhz (ne, square wave between v cc and gnd, t r =t f = 6 ns) (see fig.14) 220 mv 9.0 f max minimum frequency response ( - 3 db) 180 mhz 4.5 note 4 r l =50 w ; c l =10pf (see figs 11 and 15) 200 mhz 9.0 c s maximum switch capacitance 8 pf
1998 nov 10 13 philips semiconductors product speci?cation quad bilateral switches 74hc/hct4066 fig.10 typical switch off signal feed-through as a function of frequency. test conditions: v cc = 4.5 v; gnd = 0 v; r l =50 w ; r source =1k w . handbook, full pagewidth - 100 0 - 80 - 60 - 40 - 20 mgr263 10 10 2 10 3 10 4 10 5 10 6 (db) f (khz) fig.11 typical frequency response. test conditions: v cc = 4.5 v; gnd = 0 v; r l =50 w ; r source =1k w . handbook, full pagewidth - 5 5 0 mgr264 10 10 2 10 3 10 4 10 5 10 6 (db) f (khz)
1998 nov 10 14 philips semiconductors product speci?cation quad bilateral switches 74hc/hct4066 fig.12 test circuit for measuring crosstalk between any two switches; channel on condition. handbook, full pagewidth 0.1 m f 2r l 2r l r l v cc v i c l nz/ny ny/nz gnd channel on mgm265 fig.13 test circuit for measuring crosstalk between any two switches; channel off condition. handbook, full pagewidth 2r l 2r l 2r l v os v cc 2r l v cc c l db nz/ny ny/nz gnd mgr266 channel off handbook, full pagewidth d.u.t. 2r l 2r l 2r l v os v cc 2r l v cc v cc gnd c l oscilloscope nz/ny ny/nz gnd mgr268 ne fig.14 test circuit for measuring crosstalk between control and any switch. the crosstalk is defined as follows (oscilloscope output): f page mgr267 v(p-p)
1998 nov 10 15 philips semiconductors product speci?cation quad bilateral switches 74hc/hct4066 fig.15 test circuit for measuring minimum frequency response. adjust input voltage to obtain 0 dbm at v os when f in = 1 mhz. after set-up frequency of f in is increased to obtain a reading of - 3 db at v os . handbook, full pagewidth 0.1 m f 2r l 2r l v os v cc v is c l db nz/ny ny/nz gnd mgr269 sine-wave channel on fig.16 test circuit for measuring sine wave distortion. handbook, full pagewidth mgr270 10 m f 2r l 2r l v os v cc v is c l distortion meter nz/ny ny/nz gnd f in = 1 khz sine-wave channel on fig.17 test circuit for measuring switch off signal feed-through. handbook, full pagewidth 0.1 m f 2r l 2r l v os v cc v is c l db nz/ny ny/nz gnd channel off mgr271
1998 nov 10 16 philips semiconductors product speci?cation quad bilateral switches 74hc/hct4066 ac waveforms test circuit and waveforms fig.18 waveforms showing the input (v is ) to output (v os ) propagation delays. (1) hc: v m = 50%; v i = gnd to v cc ; hct: v m = 1.3 v; v i = gnd to 3 v. handbook, full pagewidth mgr272 v os 50% v is t r t f t plh t phl gnd v cc 90% 50% 10% fig.19 waveforms showing the turn-on and turn-off times. mga846 t plz t pzl v m (1) outputs disabled outputs enabled t pzh 90 % t phz 10 % 90 % t r t f outputs enabled ne input output low - to - off off - to - low output high - to - off off - to - high 50 % 50 % 10 % fig.20 test circuit for measuring ac performance. handbook, full pagewidth open gnd r l v is v cc v i v o mgr273 d.u.t. c l r t pulse generator v cc switch
1998 nov 10 17 philips semiconductors product speci?cation quad bilateral switches 74hc/hct4066 table 2 conditions table 3 de?nitions for figs 20 and 21: table 4 test switch v is t pzh gnd v cc t pzl v cc gnd t phz gnd v cc t plz v cc gnd others open pulse symbol definition c l load capacitance including jig and probe capacitance (see ac characteristics for values) r t termination resistance should be equal to the output impedance z o of the pulse generator t r t f = 6 ns, when measuring f max , there is no constraint on t r , t f with 50% duty factor family amplitude v m t r ;t f f max ; pulse width other 74hc v cc 50% < 2ns 6ns 74hct 3.0 v 1.3 v < 2ns 6ns fig.21 input pulse definitions. handbook, full pagewidth mgr274 t thl (t f )t tlh (t r ) v m t w positive input pulse negative input pulse 0 v amplitude 90% 10% t tlh (t r )t thl (t f ) v m t w 0 v amplitude 90% 10%
1998 nov 10 18 philips semiconductors product speci?cation quad bilateral switches 74hc/hct4066 package outlines unit a max. 1 2 (1) (1) b 1 cd (1) z ee m h l references outline version european projection issue date iec jedec eiaj mm inches dimensions (inch dimensions are derived from the original mm dimensions) sot27-1 92-11-17 95-03-11 a min. a max. b max. w m e e 1 1.73 1.13 0.53 0.38 0.36 0.23 19.50 18.55 6.48 6.20 3.60 3.05 0.254 2.54 7.62 8.25 7.80 10.0 8.3 2.2 4.2 0.51 3.2 0.068 0.044 0.021 0.015 0.77 0.73 0.014 0.009 0.26 0.24 0.14 0.12 0.01 0.10 0.30 0.32 0.31 0.39 0.33 0.087 0.17 0.020 0.13 050g04 mo-001aa m h c (e ) 1 m e a l seating plane a 1 w m b 1 e d a 2 z 14 1 8 7 b e pin 1 index 0 5 10 mm scale note 1. plastic or metal protrusions of 0.25 mm maximum per side are not included. dip14: plastic dual in-line package; 14 leads (300 mil) sot27-1
1998 nov 10 19 philips semiconductors product speci?cation quad bilateral switches 74hc/hct4066 unit a max. a 1 a 2 a 3 b p cd (1) e (1) (1) eh e ll p qz y w v q references outline version european projection issue date iec jedec eiaj mm inches 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 8.75 8.55 4.0 3.8 1.27 6.2 5.8 0.7 0.6 0.7 0.3 8 0 o o 0.25 0.1 dimensions (inch dimensions are derived from the original mm dimensions) note 1. plastic or metal protrusions of 0.15 mm maximum per side are not included. 1.0 0.4 sot108-1 x w m q a a 1 a 2 b p d h e l p q detail x e z e c l v m a (a ) 3 a 7 8 1 14 y 076e06s ms-012ab pin 1 index 0.069 0.010 0.004 0.057 0.049 0.01 0.019 0.014 0.0100 0.0075 0.35 0.34 0.16 0.15 0.050 1.05 0.041 0.244 0.228 0.028 0.024 0.028 0.012 0.01 0.25 0.01 0.004 0.039 0.016 95-01-23 97-05-22 0 2.5 5 mm scale so14: plastic small outline package; 14 leads; body width 3.9 mm sot108-1
1998 nov 10 20 philips semiconductors product speci?cation quad bilateral switches 74hc/hct4066 unit a 1 a 2 a 3 b p cd (1) e (1) eh e ll p qz y w v q references outline version european projection issue date iec jedec eiaj mm 0.21 0.05 1.80 1.65 0.25 0.38 0.25 0.20 0.09 6.4 6.0 5.4 5.2 0.65 1.25 0.2 7.9 7.6 1.03 0.63 0.9 0.7 1.4 0.9 8 0 o o 0.13 0.1 dimensions (mm are the original dimensions) note 1. plastic or metal protrusions of 0.25 mm maximum per side are not included. sot337-1 95-02-04 96-01-18 (1) w m b p d h e e z e c v m a x a y 1 7 14 8 q a a 1 a 2 l p q detail x l (a ) 3 mo-150ab pin 1 index 0 2.5 5 mm scale ssop14: plastic shrink small outline package; 14 leads; body width 5.3 mm sot337-1 a max. 2.0
1998 nov 10 21 philips semiconductors product speci?cation quad bilateral switches 74hc/hct4066 unit a 1 a 2 a 3 b p cd (1) e (2) (1) eh e ll p qz y w v q references outline version european projection issue date iec jedec eiaj mm 0.15 0.05 0.95 0.80 0.30 0.19 0.2 0.1 5.1 4.9 4.5 4.3 0.65 6.6 6.2 0.4 0.3 0.72 0.38 8 0 o o 0.13 0.1 0.2 1.0 dimensions (mm are the original dimensions) notes 1. plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. plastic interlead protrusions of 0.25 mm maximum per side are not included. 0.75 0.50 sot402-1 mo-153 94-07-12 95-04-04 w m b p d z e 0.25 17 14 8 q a a 1 a 2 l p q detail x l (a ) 3 h e e c v m a x a y 0 2.5 5 mm scale tssop14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm sot402-1 a max. 1.10 pin 1 index
1998 nov 10 22 philips semiconductors product speci?cation quad bilateral switches 74hc/hct4066 soldering introduction this text gives a very brief insight to a complex technology. a more in-depth account of soldering ics can be found in our data handbook ic26; integrated circuit packages (document order number 9398 652 90011). there is no soldering method that is ideal for all ic packages. wave soldering is often preferred when through-hole and surface mount components are mixed on one printed-circuit board. however, wave soldering is not always suitable for surface mount ics, or for printed-circuit boards with high population densities. in these situations reflow soldering is often used. through-hole mount packages s oldering by dipping or by solder wave the maximum permissible temperature of the solder is 260 c; solder at this temperature must not be in contact with the joints for more than 5 seconds. the total contact time of successive solder waves must not exceed 5 seconds. the device may be mounted up to the seating plane, but the temperature of the plastic body must not exceed the specified maximum storage temperature (t stg(max) ). if the printed-circuit board has been pre-heated, forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit. m anual soldering apply the soldering iron (24 v or less) to the lead(s) of the package, either below the seating plane or not more than 2 mm above it. if the temperature of the soldering iron bit is less than 300 c it may remain in contact for up to 10 seconds. if the bit temperature is between 300 and 400 c, contact may be up to 5 seconds. surface mount packages r eflow soldering reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. several methods exist for reflowing; for example, infrared/convection heating in a conveyor type oven. throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. typical reflow peak temperatures range from 215 to 250 c. the top-surface temperature of the packages should preferable be kept below 230 c. w ave soldering conventional single wave soldering is not recommended for surface mount devices (smds) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. to overcome these problems the double-wave soldering method was specifically developed. if wave soldering is used the following conditions must be observed for optimal results: use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. for packages with leads on two sides and a pitch (e): C larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; C smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. the footprint must incorporate solder thieves at the downstream end. for packages with leads on four sides, the footprint must be placed at a 45 angle to the transport direction of the printed-circuit board. the footprint must incorporate solder thieves downstream and at the side corners. during placement and before soldering, the package must be fixed with a droplet of adhesive. the adhesive can be applied by screen printing, pin transfer or syringe dispensing. the package can be soldered after the adhesive is cured. typical dwell time is 4 seconds at 250 c. a mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. m anual soldering fix the component by first soldering two diagonally-opposite end leads. use a low voltage (24 v or less) soldering iron applied to the flat part of the lead. contact time must be limited to 10 seconds at up to 300 c. when using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 c.
1998 nov 10 23 philips semiconductors product speci?cation quad bilateral switches 74hc/hct4066 suitability of ic packages for wave, re?ow and dipping soldering methods notes 1. all surface mount (smd) packages are moisture sensitive. depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). for details, refer to the drypack information in the data handbook ic26; integrated circuit packages; section: packing methods . 2. for sdip packages, the longitudinal axis must be parallel to the transport direction of the printed-circuit board. 3. these packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink (at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version). 4. if wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. the package footprint must incorporate solder thieves downstream and at the side corners. 5. wave soldering is only suitable for lqfp, qfp and tqfp packages with a pitch (e) equal to or larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 6. wave soldering is only suitable for ssop and tssop packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. definitions life support applications these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify philips for any damages resulting from such improper use or sale. mounting package soldering method wave reflow (1) dipping through-hole mount dbs, dip, hdip, sdip, sil suitable (2) - suitable surface mount hlqfp, hsqfp, hsop, sms not suitable (3) suitable - plcc (4) , so suitable suitable - lqfp, qfp, tqfp not recommended (4)(5) suitable - sqfp not suitable suitable - ssop, tssop, vso not recommended (6) suitable - data sheet status objective speci?cation this data sheet contains target or goal speci?cations for product development. preliminary speci?cation this data sheet contains preliminary data; supplementary data may be published later. product speci?cation this data sheet contains ?nal product speci?cations. limiting values limiting values given are in accordance with the absolute maximum rating system (iec 134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the characteristics sections of the speci?cation is not implied. exposure to limiting values for extended periods may affect device reliability. application information where application information is given, it is advisory and does not form part of the speci?cation.
internet: http://www.semiconductors.philips.com philips semiconductors C a worldwide company ? philips electronics n.v. 1998 sca60 all rights are reserved. reproduction in whole or in part is prohibited without the prior written consent of the copyright owne r. the information presented in this document does not form part of any quotation or contract, is believed to be accurate and reli able and may be changed without notice. no liability will be accepted by the publisher for any consequence of its use. publication thereof does not con vey nor imply any license under patent- or other industrial or intellectual property rights. middle east: see italy netherlands: postbus 90050, 5600 pb eindhoven, bldg. vb, tel. +31 40 27 82785, fax. +31 40 27 88399 new zealand: 2 wagener place, c.p.o. box 1041, auckland, tel. +64 9 849 4160, fax. +64 9 849 7811 norway: box 1, manglerud 0612, oslo, tel. +47 22 74 8000, fax. +47 22 74 8341 pakistan: see singapore philippines: philips semiconductors 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novembre 3, 20124 milano, tel. +39 2 6752 2531, fax. +39 2 6752 2557 japan: philips bldg 13-37, kohnan 2-chome, minato-ku, tokyo 108-8507, tel. +81 3 3740 5130, fax. +81 3 3740 5077 korea: philips house, 260-199 itaewon-dong, yongsan-ku, seoul, tel. +82 2 709 1412, fax. +82 2 709 1415 malaysia: no. 76 jalan universiti, 46200 petaling jaya, selangor, tel. +60 3 750 5214, fax. +60 3 757 4880 mexico: 5900 gateway east, suite 200, el paso, texas 79905, tel. +9-5 800 234 7381 printed in the netherlands 245106/00/03/pp24 date of release: 1998 nov 10 document order number: 9397 750 04779

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